1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to testing of integrated circuits.
2. Background of Invention
Effective testing of integrated circuits significantly enhances the ability of integrated circuit developers and manufacturers to provide reliable devices. Various techniques have been employed to test integrated circuits during the manufacturing process. One such technique that is commonly known, and has been used within the industry for over twenty years is scan testing.
Scan testing provides an efficient approach to testing the structural integrity of devices, such as flip-flops, within a complex integrated circuit. Scan testing does not test integrated circuit-level functionality. Rather, test personnel use scan testing to confirm that individual flip-flops within an integrated circuit function properly. The sheer number of flip-flops within an integrated circuit, which is often greater than a million, presents a daunting challenge for testing. Scan testing addresses this challenge through the use of automated test units that provide test vectors to scan paths including thousands of flip-flops within integrated circuits that have been designed to support scan testing.
Typically, complex integrated circuits are designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Devices, such as flip-flops, within these functional blocks can be designed, such that they can be connected together in a scan path to support scan testing. Flip-flops and other elements within a scan path include, in addition to inputs and outputs used for normal operation, two inputs associated with the scan testing capability. These include a scan input (SI) and a scan enable (SE) input. Flip-flops within a scan path have their output connected to the SI input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port. Many scan paths can exist within a single integrated circuit.
While scan testing provides significant benefits, several shortcomings exist. When a manufacturer designs an integrated circuit, many capabilities and functions are built into the integrated circuit. Not all customers will want all capabilities and functions. Rather than designing a different integrated circuit for each individual customer need, a manufacturer can include multiple functions in a circuit, and selectively enable and/or disable certain functions through different packaging. Packaging refers to how the silicon (or other material) used to create the integrated circuit is encapsulated in a protective material and what form of access is given to the integrated circuit through contact points on the packaging.
First level packaging or interconnection refers to the technology required to get electrical signals into and out of an integrated circuit—in other words the connections required between bond pads on the integrated circuit and the contact points, often pins, of the package. For example, three common types of first level packaging are wire bonding, flip chip bonding, and tape automated bonding.
The connections between a bond pad and contact point vary depending on the functions that a manufacturer wants to offer in a particular chip version. For example, when a manufacturer wants to provide a certain function, a bond pad can be connected to a contact point. Having the bond pad connected to a contact point will enable a user to access the particular feature associated with the bond pad. Conversely, a bond pad may not be connected to a contact point. In this case, the feature associated with the bond pad would not be available to a user. Alternatively, a manufacturer can couple a bond pad to ground or to a voltage source. When the bond pad is permanently coupled to a voltage source or ground, a feature is either permanently active or inactive. In this case, there is no connection between the bond pad and the contact point. When a manufacturer offers many versions of the same chip, the permutations of which bond pads are coupled to a contact point, not coupled to a contact point, coupled to ground, or coupled to a voltage source can be large.
Using different first level packaging to provide alternative versions of the same integrated circuit can significantly reduce the cost to manufacture an integrated circuit. However, this approach presents several scan testing challenges. When different first level packaging is used to produce different versions of an integrated circuit, two scan testing approaches are typically used.
The first approach is to develop test vectors for each different version of the integrated circuit and run complete scan tests for each version of the integrated circuit based on the different packaging. While providing complete tests on each integrated circuit, this approach is inefficient in that many of the same capabilities within the same base integrated circuit are being tested over and over again. In addition, developing test vectors, test set-up, and testing for each version can be prohibitively expensive.
The second approach is to run the same general purpose scan test for each version of the integrated circuit. The shortcoming of this approach is that in an integrated circuit in which a bond pad is not connected or is permanently coupled to ground or a voltage source, the scan paths associated with those bond pads can not tested. Furthermore, chip logic associated with these scan paths can also be coupled to other scan paths. Testing of those scan paths is made more difficult because the outputs from logic devices associated with scan paths that can not be tested will be an unknown or difficult to predict. Thereby, obtaining predictable results can be difficult. Thus, some flip-flops will not be tested and others will be more difficult to test.
What is needed is a circuit and methods of testing to efficiently test packaged integrated circuits in which first level packaging of an integrated circuit is varied to provide different versions of the integrated circuit.